The invention relates generally to a CMOS output buffer.
In CMOS IC's, an output buffer generally has a pull-up device to pull up the voltage on its output node and a pull-down device to pull down the output voltage on its output node. In digital circuits, the pull-up output voltage is near VDD, and the pull-down output voltage is near VSS. There are several patents relating to output buffer design, including for example: U.S. Pat. No. 5,391,939, entitled "Output Circuit of a Semiconductor Integrated Circuit"; U.S. Pat. No. 4,638,187, entitled "CMOS Output Buffer Providing High Drive Current with Minimum Output Signal Distortion"; U.S. Pat. No. 4,825,101, entitled "Full-Level Fast CMOS Output Buffer"; U.S. Pat. No. 5,189,319, entitled "Power Reducing Buffer/Latch Circuits"; and U.S. Pat. No. 5,367,205, entitled "High Speed Output Buffer with Reduced Voltage Bounce and No Cross Current".
Several conventional CMOS output buffers are shown in FIGS. 1(a-c). In FIG. 1(a), a commonly-used CMOS output buffer configuration includes a PMOS device as a pull-up transistor and an NMOS device as a pull-down transistor. The turn-on and turn-off behavior of output buffer is controlled by a prebuffer (i.e., control circuit). The prebuffer is also used to control the operational characteristics of the output buffer, e.g. producing a high-impedance state, low di/dt current, or some other special functional characteristics.
To handle the high driving or sinking currents, the output PMOS and NMOS transistors must be designed with large device dimensions and this causes the turn-on and the turn-off of the output PMOS or NMOS transistors to become very slow. Referring to FIG. 1(b), to solve this problem transient-handling circuits are added to the output buffer to improve its pull-up and pull-down operating speed. The transient-handling circuits only work within a short time duration when the output level has to be changed rapidly. The transient-handling circuits deliver the required high transient currents from either VDD or from VSS to the output node.
Alternatively, in circuits with particularly large device dimensions, complex prebuffer circuits are utilized to control the output buffer. For example, in high-speed applications, a CMOS tape buffer, such as is shown in FIG. 1(c), has been used so as to quickly drive the output buffer on or off. Even larger device dimensions of the CMOS output buffer results in having to use larger tape buffers, which in turn requires much more circuit layout area to achieve the required output functions.
In these circuits, the drains of the output PMOS and NMOS transistors are directly connected to the output pad, which is bonded to the pin of IC package. If the IC experiences an ESD (Electrostatic Discharge) event, the ESD voltage could easy cause damage to the output buffer. In submicron or deep-submicron CMOS processes, an LDD (lightly-doped drain) structure is used to overcome the hot-carrier phenomenon and a silicided diffusion is used to reduce sheet resistance of the MOS devices. But using these two advanced fabrication process techniques considerably degrades the robustness of the ESD protection of CMOS output buffer. Thus, even if the output buffer has much larger device dimensions, as a result of using these advanced CMOS processes, it is still very vulnerable to ESD stress.
Several papers have been published regarding the degradation on ESD protection reliability of CMOS IC's due to using the advanced fabrication processes. Among these papers are the following:
C. Duvvury and A. Amerasekara, "ESD: A pervasive reliability concern for IC technologies," in Proc. of IEEE, vol. 81, no. 5. pp. 690-702, May 1993. PA1 A. Amerasekara and C. Duvvury, "The impact of technology scaling on ESD robustness and protection circuit design," 1994 EOS/ESD Symp. Proc., EOS-16, pp. 237-245. PA1 C. Duvvury, et al., "ESD protection in 1-um CMOS technologies," Proc. of IRPS, pp. 190-205, 1986. PA1 C. Duvvury, et al., "ESD phenomena and protection issues in CMOS output buffer," Proc. of IRPS, pp. 174-180, 1987. PA1 C. Duvvury and R. N. Rountree, "Output ESD protection techniques for advanced CMOS process," EOS/ESD Symp. Proc., pp. 206-211, 1988. PA1 C. Duvvury and C. Diaz, "Dynamic gate coupling of NMOS for efficient output ESD protection," Proc. of IRPS, pp. 141-150, 1992. PA1 A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Devices Letters, vol. 12, pp. 21-22, 1991. PA1 M. -D. Ker, et al., "Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC," Proc.of IEEE International ASIC Conference and Exhibit, pp. 123-126, 1995. PA1 M. -D. Ker, et al., "ESD protection for deep-submicron CMOS technology using gate-couple CMO-Strigger lateral SCR structure," Technical Digest of IEEE International Electron Devices Meeting, pp. 543-546, 1995.
Because it is difficult to uniformly turn on an output transistor having large device dimensions, a gate-coupling technique, which is described in the last cited reference above, has been used to improve uniform turn-on behavior.
To summarize, having to use a CMOS output buffer of large device dimensions has two important disadvantages. One is the requirement of larger layout area, and the other is that the non-uniform turn-on behavior results in weaker ESD reliability. The present invention provides a novel solution which avoids these two disadvantages.
From a study of ESD protection circuits, it is apparent that an SCR device provides the highest ESD protection robustness in the smallest layout area. The SCR device has been successfully implemented as an ESD-protection element in CMOS IC's. Some typical references describing the use of an SCR device as ESD-protection element include the following:
In the first two of these three references, the triggering of lateral SCR device is controlled by the drain breakdown of short-channel PMOS or NMOS devices. For output ESD protection, a typical circuit, which is shown in FIG. 2, uses a PTLSCR (PMOS-Trigger Lateral SCR) device to protect the output PMOS device, and an NTLSCR (NMOS-Trigger Lateral SCR) device to protect the output NMOS device. In the third reference, the device behavior of PTLSCR and NTLSCR is more clearly explained. It also shows that the PTLSCR and NTLSCR devices can be further controlled by applying voltage to the gates of PMOS and NMOS, which are inserted into the PTLSCR and NTLSCR structures.
This invention fully uses the natural advantages of the SCR device to work as both an output device and an ESD-protection device.